Field
This invention relates to memory control sequencers, and more specifically, to memory control sequencing for frequency and power changes.
Background
Frequency and power management in a double data rate (DDR) physical (PHY) interface module is becoming increasingly complicated because the DDR-PHY has a high pin count that can result in high dynamic power. The DDR-PHY also has high frequency requirements and must transmit and receive data across a wide frequency range to support low-power DDR (LPDDR) specs. High frequency data communication is facilitated by additional high performance circuitry, on-die termination, variable voltage output high (VOH), etc. However, many of the features required to transmit and receive data at high frequency are not needed at lower frequency. Therefore, feature scaling is critical to maintaining a competitive power usage profile across frequencies. In other words, some features used to enable high frequency data communication are not necessary for low frequency data communication. In previous generations of a DDR PHY interface, different types of ad-hoc logic blocks were used to control switching between frequencies and power modes. However, adding ad-hoc control logic for frequency and power control of blocks becomes very difficult to handle due to increased complexity of the PHY interface module. The number of PHY features, and inter-dependencies between them, has grown to the extent that an easily expandable architecture is highly desirable to control these features.